The semiconductor integrated circuit industry has experienced exponential growth. In the evolution of the integrated circuit industry, functional density generally increased with reduced geometry size, and smaller and more complex circuits than the previous generation are produced. This scaling down process increases production efficiency and reduces manufacturing costs, but also complicates the manufacturing integrated circuits.
The integrated circuits are normally made through multiple process steps in a semiconductor wafer fabrication facility, where each process step places a patterned layer on a wafer. On the purpose to operate device correctly, these patterned layers must be aligned accurately with each other. Misalignment between the patterned layers may cause short circuits or connection failure, which significantly impact device yield.
Misalignment measurement between patterned layers, i.e. overlay metrology, on the wafer is one of the most important processes in the manufacturing integrated circuit devices. In particular, overlay metrology refers to the determination of the alignment accuracy of one patterned layer aligns with respect to another patterned layer next to it. With the increase in complexity of integrated circuits, the measurement of the overlay metrology becomes more and more important and difficult.